JEDEC Announces publication of e.MMC standard update v4.5
Update Defines Performance and Reliability Improvements for Embedded Mass-Storage Flash Memory Widely Used in Smart Phones and Other Mobile Devices
ARLINGTON, Va., USA – JUNE 15, 2011 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD84-B45: Embedded MultiMediaCard (eŸMMC), Electrical Standard (Version 4.5 Device). Continuing the evolution of e•MMC as an industry-leading memory standard for embedded non-volatile storage of system code, software applications and user data, the new e•MMC v4.5 standard defines functionality that focuses on improving the interaction between the host processor and the memory device at the interface, configuration and protocol levels, resulting in potential gains in overall system performance and reliability. JESD84-B45 is available for free download at http://www.jedec.org/standards-documents/results/jesd84-b45 .
eŸMMC v4.5 offers performance enhancement features, including an interface bandwidth increase from 104 Mbyte/sec to 200 MByte/sec. The command protocol is significantly improved with Packed Commands (the ability to group a series of commands in a single data transaction), Context ID (grouping different memory transactions under a single ID so the device can understand that they are related), and Data Tag (tagging specific write transactions so they can be prioritized and targeted to a memory region with higher performance and better reliability). The v4.5 standard also adds provision for volatile data cache, which can greatly reduce the latency between data transactions to improve performance.
Reliability enhancements include Power-Off Notification, which makes possible a more robust and safer power-down routine; as well as Dynamic Device Capacity, which provides a mechanism to increase device life time when the e•MMC device has reached its end-of-life, giving the user an opportunity to retrieve critical data from the device before disposal. The standard also adds the capability for the device to retrieve Real-Time Clock information from the host system, which may be used by the device internal memory management to improve data integrity and reliability.
In addition, e•MMC v4.5 provides features to better meet the requirements of the end applications, including enhanced partition attributes for system code and temporary data and separate data removal mechanisms. All performance and reliability enhancements offer designers additional options to improve system performance for the end user.
e•MMC v4.5 continues to support the current e•MMC ballout and adds a second e2MMC ballout that supports the Cache feature and 3 VDDi pins, which support an auxiliary storage medium (DRAM, Phase Change Memory, etc.) in the same device package. This enables manufacturers to fine-tune products by applying the best memory technology for a particular functionality and performance requirement.
“As mobile devices continue to require support for improved performance and reliability, JEDEC is pleased to help address the storage demands of the market with eŸMMC: a low-cost, high-performance solution,” said Mian Quddus, Chairman, JEDEC Board of Directors.
About e•MMC
Designed for a wide range of applications in consumer electronics, mobile phones, handheld computers, navigational systems and other industrial uses, eŸMMC is an embedded non-volatile memory system, comprised of both flash memory and a flash memory controller, which simplifies the application interface design and frees the host processor from low-level flash memory management. This benefits product developers by simplifying the non-volatile memory interface design and qualification process – resulting in a reduction in time-to-market as well as facilitating support for future flash device offerings. Small BGA package sizes and low power consumption make eŸMMC a viable, low-cost memory solution for mobile and other space-constrained products.
About JEDEC
JEDEC is the leading developer of standards for the solid-state industry. Over 3,000 participants, appointed by nearly 300 companies, work together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards that they generate are accepted throughout the world. All JEDEC standards are available online at www.jedec.org, at no charge.
Related Semiconductor IP
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
- High Speed Ether 2/4/8-Lane 200G/400G/800G PCS
Related News
- JEDEC Announces Publication of e.MMC Standard Update v5.0
- JEDEC Announces Publication of e.MMC Standard Update v5.1
- JEDEC Publishes Update to LPDDR5 Standard for Low Power Memory Devices
- JEDEC Publishes Update to Universal Flash Storage (UFS) Standard
Latest News
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy