Analog Bits to deliver two presentations on 16nm IP at TSMC Open Innovation Platform Ecosystem Forum
Santa Clara, CA, September 22, 2016 – Analog Bits (www.analogbits.com), the semiconductor industry’s leading provider of low-‐power mixed-‐signal IP (Intellectual Property) solutions will be presenting on two topics at the TSMC Open Innovation Platform (OIP) Ecosystem Forum. The first presentation will discuss a novel approach to keeping size small and power low, resulting in de-‐ risking SOC development while providing increased flexibility. The second presentation, delivered jointly with Mentor Graphics, will discuss design and verifications techniques for SERDES IP development on the latest 16FFC process geometry. Analog Bits will also be demonstrating the latest low-‐power mixed signal IP, including their industry leading multi-‐standard SERDES at booth 302.
WHAT: Analog Bits latest 16nm FFC Mixed Signal IP products
SERDES IP ProductsClocking IP Products
- Half-‐power SERDES IP supporting PCIe Gen 3/4, HMC 2.0, 10G-‐KR.
Sensors IP Products
- Wide range, Fine resolution and Customizable PLL & DLL IP cores
- On-‐die sensors for real-‐time monitoring of Process, Voltage and Temperature (PVT)
WHEN: September 22, 2016
13:00 -‐ 13:30: IP Track Presentation17:00 – 17:30 EDA Track Presentation
- Mahesh Tirupattur, Executive Vice President, Analog Bits
- Silicon-‐proven, low power IP for TSMC 16nm FFC for Automotive to Datacenter SOC's
10:30 – 18:30: Ecosystem Pavilion, Booth 302
- Alan Rogers -‐ President & CTO, Analog Bits
- Design and Verification of 16nm FFC Low Power SERDES for Datacenter and Automotive Applications
WHERE:
TSMC 2016 Open Innovation Platform® Ecosystem Forum
San Jose McEnery Convention Center
150 West San Carlos St. San Jose, CA 95113
About Analog Bits:
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-‐signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-‐protocol SERDES and programmable I/O’s as well as specialized memories such as high-‐speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-‐micron to 16/14-‐nm processes, Analog Bits has an outstanding heritage of "first-‐time-‐working” with foundries and IDMs.
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related News
- Analog Bits Adds New Power and Energy Management IP Blocks Proven on TSMC N2P and N3P Processes at TSMC 2025 OIP Ecosystem Forum
- Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the TSMC 2024 Open Innovation Platform Ecosystem Forum
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
- Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum
Latest News
- Quintauris and Andes Technology Partner to Scale RISC-V Ecosystem
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
- Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- TSMC September 2025 Revenue Report
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions