Altera Delivers $7 Turbo Encoder Co-processor Implementation Supporting 3GPP HSDPA Standard

San Jose, Calif., October 6, 2003—Altera Corporation (NASDAQ: ALTR) today introduced the industry’s most cost-effective turbo encoder co-processor available to support the recently established 14.4 Mbps. data throughput standard for wireless data applications.  Designers can implement the new turbo encoder MegaCore^® function using Altera’s low-cost Cyclone™ device family for as little as $7.00.

Altera’s turbo encoder implementation is supported by a reference design using a Texas Instruments (TI) TMS320C6000 digital signal processor.  The reference design simplifies the development flow by enabling the software designer to communicate from the digital signal processor to the co-processor through a basic set of application programmer interfaces (APIs). 

The latest version of the 3GPP (3^rd Generation Partnership Project) wireless standard, version 5, added a high-speed downlink packet access (HSDPA) channel to enable a dramatic increase in data transfer rates from 2 Mbps to 14.4 Mbps.  In addition, dynamic block sizing from 40 to 5114 bits must be supported every 2 ms.  This creates a significant computational burden for a digital signal processor.  Off-loading this function to a dedicated co-processor eliminates this bottleneck and frees up valuable processor bandwidth for critical system functions.

“Our turbo co-processor facilitates the integration of software and hardware during system development, thereby reducing development costs, and speeding time-to-market.  As a result, major base station vendors are working with our solution as they develop technologies to meet the new 3GPP requirements,” said Craig Lytle, vice president of Altera’s intellectual property (IP) business unit.

Turbo is a forward error correction scheme frequently used to facilitate reliable and accurate wireless transfer of data from base stations to cell phones.  It adds a code onto data prior to transmission that allows the receiving station to detect and correct any errors that may have occurred during transmission.  It became part of the 3G wireless standard in 1999.   More information on Channel Coding for HSDPA can be found at the following website:

www.altera.com/solutions/comm/wireless/3g_mobile/hsdpa/wir-hsdpa.html

Pricing and Availability
The turbo encoder MegaCore function is priced at $5,995.  Information on the core and reference design can be found at the following website:  

www.altera.com/products/ip/dsp/error_detection_correction/m-alt-turbo-enc.html

The reference design is being demonstrated at Altera’s SOPC World 2003 design
conference: www.altera.com/sopcworld.

The turbo decoder core is priced at $33,995 and information can be found at:

www.altera.com/products/ip/dsp/error_detection_correction/m-alt-turbo-dec.html.

The turbo encoder IP core can be implemented using 87 percent of Altera’s smallest Cyclone device, which has a 10k unit pricing of $8.00.  As a result, Altera customers can now implement a turbo encoder for as little as $7.00.

About the Cyclone Device Family
Cyclone devices are the industry’s lowest-cost FPGAs.  With densities ranging from 2,910 to 20,060 logic elements (LEs), Cyclone devices feature up to 288 Kbits of embedded memory and are based on a 1.5-V all-layer-copper SRAM process.  Cyclone devices offer up to two phase-locked loops (PLLs) per device and a hierarchical clocking structure for extensive on- and off-chip clock management.  For more information about the Cyclone device family, visit www.altera.com/cyclone.

About Altera
Celebrating its 20^th anniversary this year, Altera Corporation (NASDAQ: ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions.  Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.  More information is available at www.altera.com.

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