Creonic
•
HQ:
Germany
The Optical Communications Terminal (OCT) Standard was developed by the Space Development Agency (SDA) with the purpose of bringi…
- Image Conversion
Compare 22 SDA OCT IP Listing from 2 vendors
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I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
- I2C / I3C
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I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus.
- I2C / I3C
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I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) …
- I2C / I3C
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I2C Controller IP – Slave, Parameterized FIFO, AHB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP – Slave, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- NXP Rev 7.0 October 1, 2021
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I2C Controller IP – Slave, Parameterized FIFO, AXI Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 4…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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Digital Blocks, Inc.• HQ: USA
The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO)…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips/NXP – The I2C-Bus S…
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I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
Digital Blocks, Inc.• HQ: USAThe DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus …
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips/NXP – The I2C-Bus S…
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I2C Controller IP – Master / Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
Digital Blocks, Inc.• HQ: USAThe DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP – Slave, User Register Interface, No CPU Required
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal conf…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP – Master, Parameterized FIFO, AXI Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- AMBA 2.0; Philips I2C Speci…
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I2C Controller IP – Master, Parameterized FIFO, AHB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- AMBA 2.0; Philips I2C Speci…
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I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mo…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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I2C Controller IP – Master, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- AMBA 2.0; Philips I2C Speci…
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Digital Blocks, Inc.• HQ: USA
The DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- Philips I2C Specification 2…
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Digital Blocks, Inc.• HQ: USA
The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AX…
- I2C / I3C
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I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB)
Digital Blocks, Inc.• HQ: USAThe DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- NXP Rev 7.0 October 1, 2021