Analog Bits在TSMC技术研讨会上发布用于7nm的混合信号设计套件

Santa Clara, CA -- March 13, 2017 - Analog Bits (www.analogbits.com), the industry's leading provider of low-power mixed-signal IP (Intellectual Property) solutions, today announced availability of front-end design kits which enable use of low power IP on TSMC's latest 7nm process nodes. These design kits provide customers with early access to Analog Bits' latest low-power IP for SERDES, PLL, PVT sensors and POR - which are already shipping in other TSMC nodes such as 16FFC and 16FFP which will be demonstrated at the Symposium.

Multi-protocol SERDES and PVT Sensors have become an integral part of many modern SOCs, with applications including Mobile, HPC, Automotive and IoT. Analog Bits' success in delivering low-power and flexible IP means customers can get maximum differentiation in their SOC implementations.

WHAT: Complete products and 7nm front-end design kits for low-power Mixed Signal IP products including:

• Multiprotocol SERDES IP: Half-power SERDES IP supporting PCIe Gen 3/4, SAS 3/4, USB 3, Interlaken, HMC 2.0, 10G-KR.
• PLL IP: Wide range, Fine resolution and Customizable PLL & DLL IP cores
• PVT Sensor IP: On-die sensors for real-time monitoring of Process, Voltage and Temperature (PVT)

WHEN: March 15, 2017 (registration begins at 8:30am)

WHERE: 2017 TSMC Technology Symposium
Booth: 404
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

About Analog Bits:

Founded in 1995, Analog Bits, Inc. (www.analogbits.com) is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O's as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 16/14-nm processes, Analog Bits has an outstanding heritage of "first-time-working" with foundries and IDMs.