PSRAM Controller IP Listing

Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory siz…

• SRAM

Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory siz…

• SPI / QSPI XSPI
• Verified
• Available
• Supports XCCELA based PSRAM…

Our PSRAM solutions cover a range from 400Mbps to 1066Mbps, offering both normal-speed PSRAM digital IP and high-speed PSRAM mixe…

• SRAM
• Silicon Proven
• Immediate

Xccela PSRAM Memory Model provides an smart way to verify the Xccela PSRAM component of a SOC or a ASIC.

• SRAM

PSRAM Memory Model provides an smart way to verify the PSRAM component of a SOC or a ASIC.

• SRAM

In production since 2018 for many production designs.The Cadence® Memory Model Verification IP (VIP) for OctaRam provides verific…

• Verification IP

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, u…

• SPI / QSPI XSPI

DFSPI – SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and opt…

• DDR

Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.

• PHY
• XSPI

The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.

• TSMC
• 22nm
• ULL

The DDR IP Mixed-Signal MR PSRAM PHY and RPC PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC c…

• DDR

The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memo…

• SPI / QSPI XSPI

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase oper…

• SPI / QSPI XSPI
• Yes

The Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) …

• SPI / QSPI XSPI
• Pre Silicon
• Yes

The xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions.

• SPI / QSPI XSPI

The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…

• SPI / QSPI XSPI

The GMC (General Memory Controller) includes two memory controllers: The NOR/PSRAM memory controller The Synchronous DRAM (SDRAM/…

• DDR

The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity an…

• SPI / QSPI XSPI
• In Production
• Immediately