64-bit RISC-V core with in-order single issue pipeline based complex.
- CPU
64-bit RISC-V core with in-order single issue pipeline based complex.
DOME - Device Ownership Management and Enrollment
Everyday there are millions of devices that enter the IoT that contain a processor that must be maintained, monitored and securel…
IP cores for ultra-low power AI-enabled devices
Each nearbAI core is an ultra-low power neural processing unit (NPU) and comes with an optimizer / neural network compiler.
Full-featured Real-time Application Processor
The mid-range Andes Technology N10 processor is ideal for applications ranging from consumer media players and smart glasses all …
Image signal processor to advance vision systems for IoT and embedded markets
The Arm Mali-C55 image signal processor (ISP) is designed to support IoT and embedded applications where energy-efficient, high-q…
Efficient 32-bit Processor with Custom Instructions
The new Andes Technology E8 CPU processor core targets Internet of Things (IoT) applications with the unique Andes Custom Extensi…
Compact Embedded RISC-V Processor
The BA5x-CM is a feature-rich 32-bit deeply embedded processor.
A new class of machine learning (ML) processor, called a microNPU, specifically designed to accelerate ML inference in area-const…
The Synopsys USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum.
32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
32-bit RISC-V core with in-order pipeline.
Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door…
Ironwood KAP (TM) Fast, Future-Proof Key Agreement Protocol Designed for Low-Resource Devices
Key agreement protocols are at the foundation of many of today's security applications.
ChaCha20 DPA Resistant Crypto Accelerator
Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integra…
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
High Performance DDR 3/2 Memory Controller IP
This memory controller supports DDR2/3 SDRAM.
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACse…
DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throug…
LPDDR4/3 provides very intense presentation via memory controller design based on proprietary out-of-order scheduling algorithm a…