DDR IP Listing

DDR DFI Verification IP provides an smart way to verify the DDR DFI component of a SOC or a ASIC.

• Verification IP

DDR Memory Model provides an smart way to verify the DDR component of a SOC or a ASIC.

• DDR

DDR Synthesizable Transactor provides a smart way to verify the DDR component of a SOC or a ASIC in Emulator or FPGA platform.

• DDR

DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Sp…

• DDR

DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Sp…

• DDR
• In Production
• Immediately

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of …

• DDR

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managi…

• DDR

Digital ICs that interface to high speed consumer memory interfaces such as mobile DDR receive data and strobe clocks simultaneou…

• TSMC
• 55nm
• LP

DDR Assertion IP provides an efficient and smart way to verify the DDR designs quickly without a testbench.

• DDR

DDR DFI Assertion IP provides an efficient and smart way to verify the DDR DFI designs quickly without a testbench.

• DDR

Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern co…

• Single-Protocol PHY

The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…

• Single-Protocol PHY
• Silicon Proven
• Immediate

This memory controller supports DDR3/4 SDRAM.

• DDR
• In Production
• Immediate
• JEDEC standards DDR4, DDR3

Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory siz…

• SPI / QSPI XSPI
• Verified
• Available
• Supports XCCELA based PSRAM…

The Microtronix Avalon Mobile DDR SDRAM Memory Controller IP Core is designed for building high-performance Avalon-MM / Avalon-ST…

• DDR
• Available for immediate sale

Brite provides a DDR subsystem including not only controller, PHY and IO, but also corresponding tuning and configuration softwar…

• Single-Protocol PHY

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

• DDR

DDR5, DDR4, DDR3 Controller The DDR solutions, a family of high-speed on-chip interface IP, are the way for high-performance comp…

• DDR

The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…

• Single-Protocol PHY

The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…

• Single-Protocol PHY