The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
- Channel Coding
The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
Gen-Z Physical Layer for 802.3 IP Core
The IntelliProp IPC-GZ196A-ZM Gen-Z Physical Layer for 802.3 is an IP Core that allows companies to attach a Gen-Z core to an 802…
Gigabit Ethernet 802.3 MAC Controller IP
The Giga MAC IP is an embedded Fast Ethernet controller module.
50G IEEE 802.3 Reed-Solomon Forward Error Correction
Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
The 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution…
The 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet prov…
Universal Serial 10GE Media Independent Interface (USXGMII)
The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
Silicon agnostic Ethernet TSN MAC IP with speeds of 40G and 100G, based IEEE 802.3 Ethernet Layer 2 solution with support for key…
High-performance, standard-compliant, silicon-agnostic solution designed to meet the demanding requirements of data center, hyper…
Size optimized, Silicon agnostic, Silicon Proven Ethernet MAC IP core for High Speed Ethernet applications The 200G/400G Ethernet…
The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Medi…
Fast Ethernet Media Access Controller
The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements…
Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented,off-the-shelf component for the Developers …
DSP 10/100 100B-TX Ethernet PHY
SMS 10/100 ETHERNET PHY performs IEEE 802 10Base-T and 100Base-TX functionality as illustrated in Block diagram.
Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
10G XAUI/10GBase-KX4 Ethernet Verification IP
The 10G XAUI/10GBase-KX4 Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer inter…
10G TBI (PCS) Ethernet Verification IP
The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of desi…
10GBase-KR Ethernet Verification IP
The 10GBase-KR Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of d…
XGMII Ethernet Verification IP
The 10G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs …