The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
- CXL
- In production
- Available
- CXL, PCI-SIG
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
The CXL Controller IP is micro-architected with power, performance, and area optimization for high bandwidth, minimum latency, an…
Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CX…
The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®).
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…
PCIe 6.0 / CXL 3.0 PHY & Controller
The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
VIP for Compute Express Link (CXL)
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…