CXL 2.0 IP Listing

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…

• CXL
• In production
• Available
• CXL, PCI-SIG

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…

• PCIe / CXL IDE

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…

• CXL
• FPGA proven
• Immediate
• CXL V2.0

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…

• CXL
• Immediate
• CXL V2.0

The CXL Controller IP is micro-architected with power, performance, and area optimization for high bandwidth, minimum latency, an…

• CXL
• Full compliance with CXL 3.…

Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CX…

• CXL

The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.

• CXL

The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®).

• CXL

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…

• CXL
• Available on request
• Available

Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…

• CXL
• Silicon Proven

The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …

• Multi-Protocol PHY

The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.

• CXL
• Available
• CXL, PCI-SIG

Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL

The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…

• CXL