Vendor: VeriSyno Microelectronics Co., Ltd. Category: Single-Protocol PHY

USB 3.0 PHY

The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …

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Overview

The USB 3.0 PHY is a complete, mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into USB 3.0 SuperSpeed applications. The USB 3.0 PHY, usb3_sspxN_hspxN, includes all the necessary logical, geometric, and physical design files to implement complete USB 3.0 physical layer capability, connecting a USB OTG controller, host controller, or device controller to a USB system. The USB 3.0 PHY supports the USB 3.0 SuperSpeed (5 Gbps) protocol and data rate and is backward compatible with USB 2.0 high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) protocols and data rates.

Key features

  • ? 5-Gbps SuperSpeed data transmission rate through 3-m USB 3.0 cable
  • ? Spread Spectrum clock (SSC) generation and absorption
  • ? Down-spread is programmable from –4,980 ppm through 4,980 ppm
  • ? PIPE 3-compliant SuperSpeed USB 3.0 Transceiver interface
  • ? Configurable using soft PCS layer above hard macro PHY
  • ? Supports 8-bit interface at 500-MHz operation, 16-bit interface at 250-MHz operation, and 32-bit interface
  • at 125-MHz operation
  • ? Supports SuperSpeed power-down modes: U0, U1, U2, and U3
  • ? Integrated PHY includes transmitter, receiver, SSC generation, PLL, digital core, and ESD
  • ? Adaptive Rx equalization
  • ? Supports all USB 3.0 test modes
  • ? Designed for excellent performance margin and receiver sensitivity
  • ? Robust PHY architecture tolerates wide process, voltage, and temperature variations
  • ? Low-jitter PLL technology with excellent supply isolation
  • ? IEEE standards 1149.1 and 1149.6 (JTAG) boundary scan for internal visibility and control

What’s Included?

  • We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Specifications

Identity

Part Number
USB 3.0 PHY
Vendor
VeriSyno Microelectronics Co., Ltd.

Provider

VeriSyno Microelectronics Co., Ltd.
HQ: The People's Republic of China
VeriSyno Microelectronics Co., Ltd. is a national high-tech enterprise dedicated to the research and development of semiconductor IPs. The company’s main products include mixed-signal high-speed interface IPs such as USB, HDMI, DDR, MIPI, PCIe, SATA, and various analog IPs such as ADC, DAC, PLL, LVDS, as well as independently developed PSRAM interface IO solutions and vMAC series IPs. As one of the important semiconductor IP suppliers in China, in active collaboration with local foundries, VeriSyno has long been committed to the porting of those mature interface IPs to processes such as 22/28/40/55nm, to ensure secure and reliable supply of domestic IPs. The company’s diversified IP products have been widely used in industries such as industrial, medical, AI, and IoT. VeriSyno was established in September 2018 and is headquartered in Hefei, Anhui, with branch offices in Beijing, Shanghai, and Shenzhen.
Contact VeriSyno Microelectronics Co., Ltd.

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.0 PHY?

USB 3.0 PHY is a Single-Protocol PHY IP core from VeriSyno Microelectronics Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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