Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC

The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.

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TSMC 16nm FFC In Production View all specifications

Overview

The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps. It conforms with the standards of UTMI+ and PIPE4.0. The USB 3.2 Gen2X1 IP features high-speed mixed signal circuits to support Gen2 and Gen1 traffic and is backward compatible with high-speed data rates of 480Mbps, full-speed data rates of 12Mbps, and low-speed data rates of 1.5Mbps. The USB 3.2 Gen2X1 IP provides an active switch to enable bi-directional plug-in and particular functionality (such VBUS setup and USB attachment cable orientation detection) through the CC1/CC2 pins specified in the Type-C connection in order to support the USB Type-C connector.

Key features

  • Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
  • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
  • Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
  • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
  • Integrates an active switch to support the orientation-less connection with USB Type-C connector
  • Provides an auxiliary CC module IP to support USB Type-C related functions
  • Supports both wire-bond and flip-chip package type
  • Silicon Proven in TSMC 16FFC

Block Diagram

USB 3.2 Gen2 PHY IP in 16FFC block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 16nm FFC In Production

Specifications

Identity

Part Number
USB 3.2 Gen2 PHY IP in 16FFC
Vendor
T2M GmbH

Provider

T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets. T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules. With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.
Contact T2M GmbH

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC?

USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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