Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL

The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwid…

SMIC 55nm LL In Production View all specifications

Overview

The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwidth, low-power data transfers. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A separate PCS can be provided in addition to the USB 3.1 Type C PHY IP to fulfil the functions of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing. Depending on the needs of the customer, PCS is offered as a hard macro or a soft macro. The PCS standard will also be made available on its own. PHY functionality is verified by the NC-Verilog simulation tool using a test bench created in Verilog HDL..

Key features

  • Support half rate mode (5Gbps) and full rate mode (10Gbps)
  • Tolerate max +/-7000ppm input frequency offset
  • 32bit/40bit selectable parallel data bus
  • Programmable transmit amplitude
  • 3 taps/2 taps selectable FFE
  • Receiver CTLE and One-tap perspective DFE
  • Build in self-test with PRBS7/31 pattern generation and checker for production test
  • Integrated on-die termination resistors
  • Support receiver detection
  • Support LFPS signal generation and detection
  • Support Spread Spectrum clock generation and receiving
  • Flexible reference clock frequency
  • Do not need any external component
  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
  • Metal Layer:M1~M7+RDL
  • Core Voltage: 1.1V
  • IO Voltage: 3.3V
  • Silicon Proven in SMIC 55LL

Block Diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL In Production

Specifications

Identity

Part Number
USB 3.1 Type-C PHY IP in 55LL
Vendor
T2M GmbH

Provider

T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets. T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules. With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL?

USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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