Vendor: SmartDV Technologies Category: UART

UART Synthesizable Transactor

UART Synthesizable Transactor provides an smart way to verify the UART component of a SOC or a ASIC in Emulator or FPGA platform.

Contact Provider Request Datasheet

Overview

UART Synthesizable Transactor provides an smart way to verify the UART component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's UART Synthesizable Transactor is fully compliant with standard UART 16550 Specification and provides the following features.

Key features

  • Fully compatible with 16550
  • Supports transmit and receive commands allow the user to transmit and receive UART data
  • Supports additional functionality of IRDA, RS232, RS422, RS485 and GPIO
  • Supports full duplex operation
  • Supports fully configurable serial interface
  • Supports character width from 1 bit to 32 bits
  • Supports configurable baud rate
  • Supports programmable hardware flow control
  • Supports different types of parity insertion:
    • Even parity
    • Odd parity
    • Space parity
    • Mark parity
    • No parity
  • Supports number of stop bit configuration
  • Supports 16 General purpose output and input pins
  • Configurable receive FIFO depth
  • Supports constraints Randomization
  • Auto CTS/auto RTS hardware flow control
  • GPIO are supported using read and write commands
  • Supports IRDA protocol
  • Supports error injection capability:
    • Parity error
    • Framing error
  • Supports on-the-fly protocol and data checking
  • Ability to transmit strings to help verification of SOC
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations
  • UART Synthesizable Transactor comes with complete test suite to verify each and every feature of UART specification
  • Status counters for various events in bus

Block Diagram

UART Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the UART testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
UART Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about UART IP core

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

How to design secure SoCs, Part V: Data Protection and Encryption

In today’s connected world, where data is a crucial asset in SoCs, Part V of our series explores how to protect and encrypt data, whether at rest, in transit, or in use building on our earlier blog posts of the series: Essential security features for digital designers, key management, secure boot, and runtime integrity.

Not all overvoltage tolerant GPIOs are the same

Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.

Frequently asked questions about UART IP cores

What is UART Synthesizable Transactor?

UART Synthesizable Transactor is a UART IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP