UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Vendor:
SmartDV Technologies
Category:
Protocol Bridge
TileLink Synthesizable Transactor
TileLink Synthesizable Transactor provides a smart way to verify the TileLink component of a SOC or a ASIC in Emulator or FPGA pl…
Overview
TileLink Synthesizable Transactor provides a smart way to verify the TileLink component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's TileLink Synthesizable Transactor is fully compliant with standard TileLink Specification 1.8.1 and provides the following features
Key features
- Compliant with TileLink specification Version 1.8.1.
- Supports TileLink Master, TileLink Slave and TileLink Interconnect.
- Supports TileLink Uncached Lightweight (TL-UL),TileLink Uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
- Supports Cache-coherent shared memory.
- Out-of-order completion support.
- Burst fragmentation support.
- Supports constrained randomization of protocol attributes.
- Slave, Interconnect and Master support fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
- Ability to inject errors during data transfer.
- Ability to configure the width of all signals.
- Programmable Timeout insertion.
- Rich set of configuration parameters to control TileLink functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, timings and protocol violations.
- Callbacks in Master, Slave and Interconnect for various events.
- Status counters for various events on bus.
- TileLink Synthesizable Transactor comes with complete testsuite to test every feature of TileLink specification.
Block Diagram
TileLink Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV VIP's.
- All UVM sequences/testcases written with VIP can be reused.
- Runs in every major emulators environment.
- Runs in custom FPGA platforms.
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the TileLink testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
TileLink Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about Protocol Bridge IP cores
What is TileLink Synthesizable Transactor?
TileLink Synthesizable Transactor is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.