Vendor: Cadence Design Systems, Inc. Category: Protocol Bridge

Simulation VIP for PLB

In production since 2011.

Verification IP View all specifications

Overview

In production since 2011.

This Cadence® Verification IP (VIP) supports the IBM PLB standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for PLB is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. The PLB VIP supports DCR, PLB4, and PLB6, for core, devices, and bus controller.

Supported specification: PLB4 and PLB6 Specifications - IBM confidential.

Key features

  • Protocol
    • Command, read data, and write data buses - DCR, PLB4, PLB6
  • Interface
    • Core, device, snooper pin, and snoopable and non-snoopable commands - PLB4, PLB6
  • Address ordering
    • Address overlapping read/write - PLB4, PLB6
  • Cache coherency
    • Cache coherency for snoopers - PLB6
  • Data transfer
    • Supports bytes, half-word, word, or line/burst transfer - PLB4, PLB6

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for PLB
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

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Frequently asked questions about Protocol Bridge IP cores

What is Simulation VIP for PLB?

Simulation VIP for PLB is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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