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Vendor:
Cadence Design Systems, Inc.
Category:
NPU
Tensilica AI Max - NNA 110 Single Core
Single-core neural network accelerator offering from 0.5 to 4 TOPS Optimized for machine learning inference applications The Cade…
Overview
Single-core neural network accelerator offering from 0.5 to 4 TOPS Optimized for machine learning inference applications
The Cadence® Tensilica® NNA 110 accelerator incorporates a custom hardware accelerator engine (NNE) coupled with a Tensilica Vision P6 or P1 DSP. The specialized compute block inside the NNA 110 hardware leverages features like random sparsity, tensor compression / decompression to provide an overall best in-class embedded AI accelerator solution.
A single-core NNA 110 accelerator supports 256 to 2K MAC 8x8-bit MAC computations and has various user-defined configurable options. The NNA 110 accelerator can run all neural network layers, including but not limited to convolution, fully connected, LSTM, LRN, and pooling operations. The accompanying Tensilica DSP in NNA 110 can run any operation that is not native to the accelerator, thereby making NNA 110 a highly flexible and robust future-proof offering. NNA 110 solution deliverables comprises of turnkey soft RTL IP, software compiler toolchain, and an accurate simulator for benchmarking.
The Cadence® Tensilica® NNA 110 accelerator incorporates a custom hardware accelerator engine (NNE) coupled with a Tensilica Vision P6 or P1 DSP. The specialized compute block inside the NNA 110 hardware leverages features like random sparsity, tensor compression / decompression to provide an overall best in-class embedded AI accelerator solution.
A single-core NNA 110 accelerator supports 256 to 2K MAC 8x8-bit MAC computations and has various user-defined configurable options. The NNA 110 accelerator can run all neural network layers, including but not limited to convolution, fully connected, LSTM, LRN, and pooling operations. The accompanying Tensilica DSP in NNA 110 can run any operation that is not native to the accelerator, thereby making NNA 110 a highly flexible and robust future-proof offering. NNA 110 solution deliverables comprises of turnkey soft RTL IP, software compiler toolchain, and an accurate simulator for benchmarking.
Key features
- Supports scalable NNE MAC configurations: 256, 512, 1024, and 2048 8-bit MACs (# of 16-bit MACs = 1/4th of # 8-bit MACs)
- Supports UBUF configurations: 256KB to 2MB
- Supports various bandwidth configurations: 32/16/8/4 bytes/clock and AXI bus width of 128 or 256 bits
- Supports clock rates up to 1GHz
- Run-time sparsity-based cycle speedup
- 4-bit weight clustering
- Runtime tensor bandwidth compression/decompression
- Asymmetric quantization support
Block Diagram
Tensilica AI Max - NNA 110 Single Core block diagram
Applications
- Automotive,
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace,
- Others
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
Tensilica AI Max - NNA 110 Single Core
Vendor
Cadence Design Systems, Inc.
Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
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Frequently asked questions about NPU IP cores
What is Tensilica AI Max - NNA 110 Single Core?
Tensilica AI Max - NNA 110 Single Core is a NPU IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this NPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.