SPI (Serial Peripheral Interface) Verification IP

SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI basic protocol as defined in Motorola's M68HC11 user manual rev 5.0. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI (Serial Peripheral Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI (Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Follows SPI basic specification as defined in SPI Block Guide V04.01
• Supports SQI interface specification and common flash device models
• Supports data width from 4 bits to 64 bits.
• Supports Master and Slave Mode
• Supports 3-wire, 4-wire SPI interface
• Supports bus width 1 bit and 4 bit
• Slave device supported for SPI 3 wire are
• BOSCH SMB380
• RICOH R2033K
• Supports baud rate selection
• Supports internal clock division check.
• Supports clock polarity (CPOL) selections.
• Supports clock phase (CPHA) selection.
• Supports single and burst transfer mode.
• Supports on the fly generation of data.
• Supports daisy-chaining connection.
• Supports Glitch insertion and detection
• Detects and reports the Mode Fault error
• Supports customized single/dual/quad modes for Command, Address and Data phase.
• Supports configurable dummy cycles.
• Supports configurable memory density.
• Supports backdoor access for memory and registers.
• Built in functional coverage analysis.
• Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI bus.
• SPI Slave can be configured as standard device or can use FIFO for data passing.
• In standard model mode, Mater/Slave support different types of devices. Like FLASH, EEPROM, FRAM,RTC,SQI,MOTOROLA Mode,NS mode and TI mode(PRECEDE and cOINCIDE), EMPSPI, MACRONIX, DBI TYPE C, Serial flash and MAXIM.
• Supports single,dual and quad mode bus width operation
• Supports spansion DDR model
• Master contains rich set of commands for both standard device and FIFO model mode.
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
• SPI Verification IP comes with complete test suite to test every feature of SPI specification.

• Faster testbench development and more complete verification of SPI designs.
• Easy to use command interface simplifies testbench control and configuration of slave and master.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the SPI testcases.
• Examples showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.