Vendor: Cadence Design Systems, Inc. Category: SPDIF

Simulation VIP for SPDIF

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol pro…

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Verification IP View all specifications

Overview

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPDIF helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: Indian Standard DIGITAL AUDIO INTERFACE PART 3 CONSUMER APPLICATIONS (IEC 60958-1)

Key features

  • Maximum Audio Sample Word Length
    • Supports both 20-bit and 24-bit audio word length format. In 20-bit audio word length format, AUX field will be present
  • Audio Sample Word Length
    • Supports padding in audio data if audio sample word length is less than the maximum audio word length
  • Parity Generation
    • Generates parity internally
  • Preamble Error Injection
    • Transmits erroneous preamble

Block Diagram

Simulation VIP for SPDIF block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Simulation VIP for SPDIF
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Learn more about SPDIF IP core

Growing audio requirements in SoCs

As consumer devices such as tablets, media players and home theater systems continue to incorporate more audio functionality, the systems on chip (SoCs) designed for these devices become more complex. These SoCs must support a growing list of audio requirements such as a wider range of high-definition audio compression formats, multi-channel audio content, higher sampling rates and advanced audio post-processing functions.

Frequently asked questions about S/PDIF IP cores

What is Simulation VIP for SPDIF?

Simulation VIP for SPDIF is a SPDIF IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this SPDIF?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPDIF IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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