Vendor: SmartDV Technologies Category: SPDIF

SPDIF Synthesizable Transactor

SPDIF Synthesizable Transactor provides an smart way to verify the SPDIF component of a SOC or a ASIC in Emulator or FPGA platfor…

Overview

SPDIF Synthesizable Transactor provides an smart way to verify the SPDIF component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's SPDIF Synthesizable Transactor is fully compliant with IEC 60958 Specification and provides the following features.

Key features

  • Supports full SPDIF functionality as per specs IEC 60958 and IEC 61937
  • Supports SMPTE 337M standards for non Linear PCM Audio
  • Supports AES/EBU, AES3 standards for Linear PCM Audio
  • Supports following sampling/driving rates,
    • 32 kHz
    • 22.05 kHz
    • 24 kHz
    • 768 kHz
    • 384 kHz
    • 352.8 kHz
    • 1536 kHz
    • 44.1 kHz
    • 48 kHz
    • 88.2 kHz
    • 96kHz
    • 176.4 kHz
    • 192 kHz
  • Supports 32 audio channels.
  • Configurable Baud rate control.
  • Supports the Biphase-mark code.
  • Supports start bit correction.
  • Supports clock recovery circuit.
  • Supports injection of various errors
    • Preamble error
    • Channel status error
    • Parity Error
    • Various field errors
  • SPDIF Synthesizable Transactor comes with complete testsuite to verify each and every feature of SPDIF specification.
  • On-the-fly protocol and data checking.
  • Supports programmable FIFO depth.

Block Diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the SPDIF testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SPDIF Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about SPDIF IP core

Growing audio requirements in SoCs

As consumer devices such as tablets, media players and home theater systems continue to incorporate more audio functionality, the systems on chip (SoCs) designed for these devices become more complex. These SoCs must support a growing list of audio requirements such as a wider range of high-definition audio compression formats, multi-channel audio content, higher sampling rates and advanced audio post-processing functions.

Frequently asked questions about S/PDIF IP cores

What is SPDIF Synthesizable Transactor?

SPDIF Synthesizable Transactor is a SPDIF IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this SPDIF?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPDIF IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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