Configurable SPDIF-AES3 Receiver
The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds …
Overview
The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds hardware support for the IEC61937 and SMPTE 337M standards for non-PCM (compressed) audio. This purely digital clock and data recovery method dispenses the classical analog PLL at the input reducing the receiver cost. The Modular structure of the CWda14 allows enhanced functionality for specific applications by using the optional Add-on-Modules (AOM). Coreworks offers a broad range of SPDIF receivers and transmitters targeted for variety of audio applications.
Key features
Specifications
- Supports the SPDIF (IEC60958) and AES3 standards for stereo PCM audio transmission
- Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission (Dolby Digital, AAC, DTS, MPEG, etc)
- Digitally de-jitters recovered clock and outputs a good quality audio retransmission clock
- Automatic removal of stuffing bits in non-PCM mode
- Average 0.6 sample periods (0.6/Fs) lock time
- System clock (fclk) minimum required frequency Ffclk = 420*Fs for Fs = 96kHz or lower, or Ffclk = 640*Fs for Fs = 192 kHz
- Optional separate interfaces for data and control
- Optional channel Status and User bits memory mapped buffers
- Programmable FIFO level trigger
- Configurable endianness for both control and data interfaces
- Measures and reports input signal sample rate
- Optional AMBA® AHB master interface with embedded DMA controller and memory ping-pong buffers
- I2S output port
Interfaces
- AMBA-APB, AMBA-AHB or parallel interface for configuration, control and status
- SPDIF/AES3 interface for audio input
- AMBA-APB, AMBA-AHB or parallel interface for audio output
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about SPDIF IP core
A configurable FPGA-based multi-channel high-definition Video Processing Platform
Using FPGAs to interface with digital communication protocols
Optimizing the Implementation of Dolby Digital Plus in SoC Designs
One Approach to IP Cores: Ten Years and Going Strong
Timing key to optimizing audio performance in consumer products
Frequently asked questions about S/PDIF IP cores
What is Configurable SPDIF-AES3 Receiver?
Configurable SPDIF-AES3 Receiver is a SPDIF IP core from Coreworks, S.A. listed on Semi IP Hub.
How should engineers evaluate this SPDIF?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPDIF IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.