MPCIE Verification IP

MPCIE Verification IP provides an smart way to verify the PCIE bi-directional bus. The SmartDV's MPCIE Verification IP is fully compliant with version 1.0/2.0/3.0/4.0/5.0 of the PCIE Specification and provides the following features

MPCIE Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MPCIE Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports PCIE Express specs 1.0/2.0/3.0/4.0/5.0
• Supports MPHY RMMI and serial interface
• - > All error injections in MPHY layer
• - > All protocol checks for MPHY layer
• - > All PWM and HS gears as supported by MPCIe
• - > All lane configurations as supported by MPCIe
• - > Automatic clock recovery for HS mode
• Supports asymmetrical lane configuration
• Supports dynamic bandwidth scalability as per specs
• Supports both Rate A and Rate B
• Supports UVM and Verilog APIs supplied , as well as C DPI exports
• Supports Full link speed and width negotiation up to 32 Lanes
• Supports Automated Error Injections at all layers.
• Supports Checkers verify protocol timing checks and functional accuracy at each layer
• Supports Queuing for 8 VCs with configurable depth
• Supports Configurable TC to VC queue mapping
• Supports for multiple Requestor / Completer applications, including user supplied applications
• Supports Checks all TLPs for correct formation of headers, prefixes, and ECRC
• Supports Full DL state machines
• Supports Checks all framing, LCRC, and lane rules
• Supports Check all DLLP fields and formatting
• Supports ASPM and Software controlled Power Management
• Supports Automated Error Injections and checking
• Supports Full LTSSM state machine
• Supports SERDES model with digital clock recovery
• Supports Speed and Link Width negotiation
• Supports Upconfigure, polarity inversion, and lane-to-lane skew
• Supports 8b/10b encoding
• Supports Configurable timers and timeouts
• Callbacks in Root complex,End point and monitor for user processing of data
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
• MPCI Express Verification IP comes with complete testsuite to test every feature of PCI Express specification
• Supports scoreboard checking
• Built-in monitors for protocol checking, including a global bus monitor
• Functional coverage to cover all functionality of MPCIE Root complex and End point
• Supports multiple instantiations to create complex verification environment
• Supports Scaled Flow control
• Supports Data Link Feature Exchange
• Supports VF 10-Bit Tag Requester
• Supports Enhanced Allocation
• Supports Emergency Power Reduction State
• Supports Alternate Routing-ID Interpretation
• Supports Protocol Multiplexing

• Faster testbench development and more complete verification of MPCI Express designs
• Easy to use command interface simplifies testbench control and configuration of Root complex and End point
• Simplifies results analysis
• Runs in every major simulation environment

• Complete regression suite containing all the MPCIE testcases to certify MPCI Express Root complex and End point
• Examples showing how to connect various components, and usage of BFM and Monitor
• Detailed documentation of all class, task and function's used in verification env
• Documentation also contains User's Guide and Release notes