Vendor: SmartDV Technologies Category: MIPI

MIPI DigRF Verification IP

MIPI DigRF Verification IP is compliant with MIPI DigRF specification and verifies DigRF devices.

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

MIPI DigRF Verification IP is compliant with MIPI DigRF specification and verifies DigRF devices. DigRF Verification IP is developed by experts who have worked on complex protocols before.

MIPI DigRF Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI DigRF Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports 1.2 MIPI DIGRF Specification.
  • Supports both Data and Control frames
  • Supports frames nesting
  • Supports up to four lanes
  • Supports distribution and merging data over lanes
  • Supports programmable sync pattern and length
  • Supports LS,HS1,HS2 modes
  • Supports HIBERNATE mode
  • Supports LOOPBACK and CLOCK TEST mode
  • Supports byte striping
  • Supports ARQ scheme(NACK only)
  • Supports ARQ scheme disable
  • Supports frames retransmission
  • Supports dummy frames retransmission
  • Supports lane insertion
  • Includes the MIPI M-PHY VIP for physical layer verification
    • Automatic Link Training
    • Low speed and High speed operation
  • Supports various types of frame errors
    • CRC error
    • Wrong CRI error
    • Various fields corruption error
  • Supports RMMI 10/20/40 Bit interfaces
  • Support following 8b/10b error insertion and detection
    • Invalid K character injection
    • Injection of disparity errors
    • Wrong K character injection
    • Corruption of Marker characters
  • Monitor,Detects and notifies the testbench of all protocol and timing errors.
  • Supports constraints Randomization.
  • Status counters for various events in bus.
  • Callbacks in transmitter and receiver for various events.
  • MIPI DigRF Verification IP comes with complete test suite to test every feature of MIPI DigRF specification.
  • Functional coverage for complete MIPI DigRF features.

Block Diagram

MIPI DigRF VIP block diagram

Benefits

  • Faster testbench development and more complete verification of MIPI DigRF designs.
  • Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the MIPI DigRF testcases.
  • Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
MIPI DigRF VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about MIPI IP core

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is MIPI DigRF Verification IP?

MIPI DigRF Verification IP is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP