Vendor: Cadence Design Systems, Inc. Category: USB

Simulation VIP for eUSB2V2

Best-in-class eUSB2v2 Verification IP for your IP, SoC, and system-level design testing.

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Overview

Best-in-class eUSB2v2 Verification IP for your IP, SoC, and system-level design testing.

The Verification IP (VIP) for eUSB2v2 is a complete VIP solution for the embedded USB2 (eUSB2) version 2.0. It provides a mature and comprehensive verification IP (VIP) for the eUSB2v2 protocol. Incorporating the latest protocol updates, the eUSB2v2 VIP is not only a complete bus functional model (BFM) for the eUSB2v2 DUT, but it also provides integrated automatic protocol checks and coverage models.

This VIP for eUSB2v2 provides support for any agent in native mode: host (eDSPn) or device (eUSPn). It supports eUSB2v2 operational high speed (960Mbps to 4.8Gb/s). eUSB2v2 link can be configured as symmetric or asymmetric, each with multiple bit rate options (960Mbps to 4.8Gb/s in both transfer directions). The eUSB2v2 VIP is designed to make it easy to integrate into a testbench for IP, system-on-chip (SOC), and subsystem-level. The eUSB2v2 VIP helps reduce the time to test by accelerating verification closure and ensuring end-product quality.

The VIP for eUSB2v2 runs on all major simulators. It supports all main verification languages, such as Verilog, SystemVerilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specifications: eUSB2v2 1.0

Key Features

The following are the key features from the specifications that are implemented in the VIP:

Feature Name

Description

Supported DUT Types
  • All eUSB2v2-compliant DUT types in host (eDSPn) or device (eUSPn) mode

Transaction Types
  • All types of transfers: bulk, control, interrupt, and isochronous transactions

Enumeration
  • Provides a complete USB protocol hierarchy enumeration process for device models from Host

Operational Speed
  • Operates at high speed (960Mbps to 4.8Gb/s) and support symmetric/asymmetric data rate

Reset Signaling
  • Supports high-speed chirp handshake

Suspend/Resume
  • Supports suspend, resume, remote wake-up, and low-power management (LPM)

Transaction and Packet Checks
  • Checks for all transaction and packet rules including inter-packet gap and propagation delays

Protocol Features
  • Support symmetric/asymmetric mode: All HSx data rate for upstream and downstream supported
  • Support scrambling
  • Support link bring up
  • Support for jitter handling
  • Support for port reset in all states
  • Supports improved ISOC transfer with up to three data packets per OUT/IN token
  • Bulk transfer with data packet 1024 is supported

Translator
  • Digital translator available for sending eUSB2v2-compliant traffic

Register interface
  • Support to change the severity (Error, Warning, Info) of the protocol assertions
  • Support to initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on
  • Support to control the functionality such as end-point buffers, chirp sequence, and clock frequency
  • Support to store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench
  • Support to insert error injections
  • Support to initiate go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)

Predefined Error Injections
  • Device drives Port Reset during POR
  • Host drive ED+ as 1 instead of driving SE1 in Port Reset
  • Device corrupts the ACK in Port Configuration
  • Device drives invalid Connect Signal depending on the speed of operation
  • Device drives invalid ping
  • Host does not send an EOP
  • Host drives J signal instead of K during the resume operation
  • Host does not drive Resume signal after Remote wakeup from device
  • Host sends corrupted EOP to the device

Block Diagram

Simulation VIP for eUSB2V2 block diagram

Benefits

  • Supports testbench languages for SystemVerilog, UVM, OVM, and e
  • Runs on all major simulators
  • Generation of constraint-random bus traffic
  • Verify all agent types: host (eDSPn) or device (eUSPn)
  • Dynamic activation and reconfigure the VIP attributes anytime during the simulation
  • Built-in verification plan, protocol checks, and coverage model
  • Callback access at multiple TX and RX queue points for scoreboard and data manipulation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for eUSB2V2
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about USB IP cores

What is Simulation VIP for eUSB2V2?

Simulation VIP for eUSB2V2 is a USB IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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