Vendor: Cadence Design Systems, Inc. Category: Protocol Bridge

Simulation VIP for AMBA AXI

Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI specification which is part of the Arm® AMBA® famil…

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Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for AXI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC and performance analysis that provides automated generation of testbenches. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: AMBA 3 AXI, AMBA 4 AXI, AMBA 4 AXI-Lite, AMBA 5 AXI, and AMBA 5 AXI-Lite interfaces, AMBA AXI issues F, G, and H.

Key features

  • Multiple Agents
    • Supports any number of agents
  • Data and Address Widths
    • All legal data and address widths
  • Additional Signaling
    • AxQOS, AxREGION, and user-defined signals introduced in AMBA4 AXI
  • AXI-Lite
    • AXI-Lite configuration, automatically modifies the agent's behavior accordingly
  • Automatic Subordinate Responses
    • Support to use automatic Subordinate responses
  • Transmission Order Control
    • Controls the order of transmission of write transfers (AMBA 3 AXI only), read transfers, and write responses
  • Data Before Address
    • Sending of data before address transactions when legal
  • Delay Control
    • Control the delay between the items on the channels
  • Exclusive Access
    • Monitoring and driving of all exclusive transactions
  • Locked Transactions
    • Monitoring and driving of locked transactions (AMBA 3 AXI only)
  • Manager Signal Control
    • Control the values of the burst signals in the read and write address channel and transfer signals in the write data channel
  • Subordinate Response Control
    • Control over the values of the signals in the read data channel
  • Transaction Types
    • Monitoring and driving of all read and write transactions
  • Atomic Transactions
    • Atomic transactions in AMBA 5 AXI
  • Other Signaling
    • User Loopback Signaling, QoS Accept Signaling and Wake-Up Signaling
  • Trace Signals
    • Applicable to AXI5 and AXI5-Lite
  • Untranslated Transactions
    • Support for Untranslated Transactions
  • Non-Secure Access Identifiers
    • Support for Non-Secure Access Identifiers
  • MPAM
    • Memory Partitioning and Monitoring functionality
  • MTE
    • Memory Tagging Extensions functionality

Block Diagram

Simulation VIP for AMBA AXI block diagram

Specifications

Identity

Part Number
Simulation VIP for AMBA AXI
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about Protocol Bridge IP cores

What is Simulation VIP for AMBA AXI?

Simulation VIP for AMBA AXI is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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