Vendor: Cadence Design Systems, Inc. Category: Debug Trace

Simulation VIP for AMBA ATB

Cadence provides a mature and comprehensive Verification IP (VIP) for the Trace Bus (ATB) specification which is part of the Arm®…

Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the Advanced Trace Bus (ATB) specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for ATB provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the system and performance analysis that provides automated generation of testbenches. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for ATB helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA4 ATB v1.0 and v1.1.

Key features

  • Data Widths
    • All legal data widths
  • Automatic Subordinate Responses
    • Support to use automatic Subordinate responses
  • Delay Control
    • Control the delay between the items on the channels
  • Manager Signal Control
    • Control the values of the signals issued by the manager
  • Subordinate Response Control
    • Control over the values of the signals issued by the subordinate
  • Multiple Agents
    • Supports any number of agents
  • Transaction Types
    • Monitoring and driving of all transactions (data, flush, and sync)

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for AMBA ATB
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

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Frequently asked questions about Debug Trace IP

What is Simulation VIP for AMBA ATB?

Simulation VIP for AMBA ATB is a Debug Trace IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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