AMBA ATB Verification IP
AMBA ATB Verification IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC.
Overview
AMBA ATB Verification IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC. The SmartDV's AMBA ATB Verification IP is fully compliant with standard AMBA ATB Specification. Our AMBA ATB VIP is proved across multiple customers.
AMBA ATB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA ATB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Compliant to ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Protocol.
- Support AMBA ATB Master, ATB Slave, ATB Monitor and ATB Checker.
- Support for multiple masters and slaves.
- Supports all ARM AMBA ATB data, byte and ID widths.
- ATB 1.0/ATB 1.1 common support
- Supports Flow control - valid/ready signaling for trace data.
- Supports Flush Request Response control - Flush valid/ready signaling with trace data.
- Supports capturing of valid trace data.
- Supports master internal buffer storage,configurble of trace sources to store trace locally or not.
- Supports constrained randomization of protocol attributes.
- Flexibility to send completely configured data.
- Programmable ID's for the trace transfers.
- Programmable Timeout insertion.
- Ability to inject errors during data transfer.
- ATB 1.1 support
- In addition to ATB 1.0 support, ATB 1.1 supports the following features,
- Supports enable and disable access for clock.
- Supports Synchronization Request operations.
- Supports triggering operations.
- Supports FIFO memory.
- Rich set of configuration parameters to control ATB functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in master, slave and monitor for various events.
- Status counters for various events on bus.
- ATB Verification IP comes with complete testsuite to test every feature of ARM AMBA ATB specification
Block Diagram
Benefits
- Faster testbench development and more complete verification of AMBA ATB designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the AMBA ATB testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Debug Trace IP
What is AMBA ATB Verification IP?
AMBA ATB Verification IP is a Debug Trace IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Debug Trace?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.