Vendor: Truechip Solutions Category: SENT

SENT Verification IP

The SENT Verification IP provides an effective & efficient way to verify the SENT components of an IP or SoC.

Overview

The SENT Verification IP provides an effective & efficient way to verify the SENT components of an IP or SoC. The SENT VIP is fully compliant with SENT Specification SAE J2716. The VIP is light weight with easy plug-and-play components so that there is no hit on the design cycle time.

Key features

  • Adherent to Single Edge Nibble Transmission (SENT) SAE J2716.
  • Supports Both Slow and Fast Channel Transmission
  • Supports Following Types of Frames for SLOW channel Transmission
    • Short Serial Message Format
    • Enhanced Serial Message Format
  • Supports Following Types of Frames for Fast Channel Transmission
    • Two 12-bit fast channels (6 data nibbles)
    • One 12-bit fast channel (3 data nibbles)
    • High Speed with one 12-bit fast channel (4 data nibbles)
    • Secure Sensor with 12-bit fast channel 1 and secure sensor information on fast channel 2 (6 data nibble)
    • Single Sensor with 12-bit fast channel 1 and zero value on fast channel 2 (6 data nibble)
    • Two fast channels with 14-bit fast channel 1 and 10-bit fast channel 2 (6 data nibble)
    • Two fast channels with 16-bit fast channel 1 and 8-bit fast channel 2 (6 data nibble)
  • Supports Enhanced serial message formats with different configurations
    • 12-bit data and 8-bit message ID
    • 16-bit data and 4-bit message ID
  • Supports Configuration of nodes as Sensor, Active or Passive Device.
  • Supports programmable clock frequency of operation.
  • Supports pause pulse properties
    • Minimum length 12 ticks
    • Maximum length 768 ticks
  • Supports all types of error insertion and detection.
    • Checksum errors l Message ID errors
    • Oversize errors
    • Sync errors
  • Supports Glitch insertion and detection.
  • Functional coverage for complete SENT features.
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • SENT Verification IP comes with complete test suite to test every feature of SENT specification SAE J2716.

Block Diagram

Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity examples for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solutions and easy integration in IP and SoC environment

What’s Included?

  • SENT Sensor/Device/BFM/Agent
  • SENT Monitor
  • SENT Scoreboard
  • Testbench Configurations
  • Test Suite (Available in Source code)
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual and Release Notes

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SENT / LIN
Vendor
Truechip Solutions

Provider

Truechip Solutions
HQ: USA
Truechip is a leading provider of Design and Verification solutions – which help you to accelerate your design, lowering the cost and the risks associated in the development of your ASIC, FPGA and SoC. Truechip is a privately held company, with a global footprint and with a strong and experienced leadership team. Truechip was established in 2008 with a Mission to:
  • To create world class Verification IP Solutions
  • To provide expert consultancy to ASIC & SoC Design companies
  • To design SOCs from Architecture to Working Silicon
Our Vision is to:
  • To be the leading provider of Semiconductor IP Solutions
  • To be a one-stop-shop for Design and Verification
Our Guiding Principles are:
  • Customer Success
  • Commitment to Quality
    • Quality of Products
    • Quality of Engineers
  • Best in class Customer Support
  • Ethics and Integrity
We at Truechip leverage the extensive domain knowledge and expertise from current associations to provide complete set of design and verification solutions to our customers.

Learn more about SENT IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2

Integrating PQC into a widely deployed IKEv2 implementation is an important step toward making secure communication future-proof. We integrated ML-KEM, the NIST-standardized module-lattice KEM, into StrongSwan’s IKEv2 stack using our own KiviPQC-KEM hardware accelerator.

VESA Adaptive-Sync V2 Operation in DisplayPort VIP

In a computer system, both the GPU as well as the monitor have a certain rate at which they render or update an image, respectively. The rate is nothing but the frequency at which the image is refreshed (updated in the image it shows/displays), usually expressed in hertz, and can vary based on the content displayed on the screen.

Frequently asked questions about SENT IP cores

What is SENT Verification IP?

SENT Verification IP is a SENT IP core from Truechip Solutions listed on Semi IP Hub.

How should engineers evaluate this SENT?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SENT IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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