Vendor: SmartDV Technologies Category: SENT

SENT (SAE J2716) Synthesizable Transactor

Single Edge Nibble Transmission (SENT) is a single-wire, serial unidirectional communication protocol.

Contact Provider Request Datasheet

Overview

Single Edge Nibble Transmission (SENT) is a single-wire, serial unidirectional communication protocol. It is intended for use in applications where high resolution sensor data needs to be communicated from a sensor to an Engine Control Unit (EUC). It is intended as a replacement or the lower resolution methods of 10 bit A/D's and as a simpler low cost alternative to CAN or LIN in automotive industry. SENT VIP are reusable components that provide ready made verification environment. Compatible with Single Edge Nibble Transmission (SENT) specifications and supports all the frame types. SAE J2716 includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.

Key features

  • Compatible with Single Edge Nibble Transmission (SENT) specification SAE J2716 JAN2010
  • Supports SENT/SPC protocol as defined in the MPC5510 Microcontroller family (AN4219)
  • Supports all types of frames
    • Short Serial Message format
    • Enhanced Serial Message format
  • Enhanced serial message formats Supports different configurations
    • 12-bit data and 8-bit message ID
    • 16-bit data and 4-bit message ID
  • These SAE J2716 nodes can be configured as Sensor, Active Device or Passive Device nodes
  • The DUT can either be a SAE J2716 sensor or device
  • Supports programmable clock frequency of operation
  • Built-in checkers ensures that SAE J2716 Protocol has been followed correctly
  • Supports all types of error insertion and detection
    • Checksum error
    • Message ID error
    • Oversize error
    • Sync error
  • Supports pause pulse properties
    • Minimum length 12 ticks
    • Maximum length 768 ticks
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

SENT (SAE J2716) Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the SAE J2716 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SENT (SAE J2716) Transactor
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about SENT IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2

Integrating PQC into a widely deployed IKEv2 implementation is an important step toward making secure communication future-proof. We integrated ML-KEM, the NIST-standardized module-lattice KEM, into StrongSwan’s IKEv2 stack using our own KiviPQC-KEM hardware accelerator.

VESA Adaptive-Sync V2 Operation in DisplayPort VIP

In a computer system, both the GPU as well as the monitor have a certain rate at which they render or update an image, respectively. The rate is nothing but the frequency at which the image is refreshed (updated in the image it shows/displays), usually expressed in hertz, and can vary based on the content displayed on the screen.

Frequently asked questions about SENT IP cores

What is SENT (SAE J2716) Synthesizable Transactor?

SENT (SAE J2716) Synthesizable Transactor is a SENT IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this SENT?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SENT IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP