eDisplay Port/Display Port v1.4 IP Listing

The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption.

• SMIC
• 40nm
• LL
• In Production

eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.

• TSMC
• 22nm
• ULP
• In Production

The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver.

• TSMC
• 28nm
• HPC+
• In Production