Vendor:
SmartDV Technologies
Category:
SPI / QSPI XSPI
SafeSPI Verification IP
SafeSPI is the serial synchronous communication protocol based Flash VIP, supporting all major SafeSPI vendors.
Overview
SafeSPI is the serial synchronous communication protocol based Flash VIP, supporting all major SafeSPI vendors. SafeSPI Verification IP can be used to verify SafeSPI Master or Slave in SOC. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
SafeSPI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SafeSPI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports 100% of SafeSPI protocol Standards.
- Supports bit encodings
- Supports all SPI Transfers as per the Specification
- Supports all SafeSPI Timing Standards.
- Supports in-frame and out-of-frame communication
- Supports CRC calculation for in-frame and out-of-frame command/response.
- Supports backdoor access for memory and registers
- Built in functional coverage analysis.
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SafeSPI bus.
- SafeSPI Slave can be configured as standard device or can use FIFO for data passing.
- Master contains rich set of commands for both standard device and FIFO model mode.
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
- SafeSPI Verification IP comes with complete test suite to test every feature of SafeSPI specification.
Block Diagram
SafeSPI VIP block diagram
Benefits
- Faster testbench development and more complete verification of SafeSPI designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment
What’s Included?
- Complete regression suite containing all the SafeSPI testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
Specifications
Identity
Part Number
SafeSPI VIP
Vendor
SmartDV Technologies
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is SafeSPI Verification IP?
SafeSPI Verification IP is a SPI / QSPI XSPI IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.