Quadrature former 75-750 MHz
This device is designed to generate a quadrature heterodyne (oscillator) signal.
Overview
This device is designed to generate a quadrature heterodyne (oscillator) signal. CML logic quadrature generator consists of pre-switchable divider with the division factor 1, 2, 4, 8, divider by 2, divider by 4 that form quadrature signal, output signal (to the input) strobbing block, and phase adjustment block implemented on signal delay time.
Key features
- TSMC CMOS 65 nm
- Output frequency range 75-750 MHz
- Input signal division (by 8, 16, 32 or 64)
- High accuracy of the phase control
- Operating-temperature range: from -40 °C to + 125 °C
Block Diagram
Applications
- Quadrature signal processing for mixer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | GP | Silicon Proven |
Specifications
Identity
Provider
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Frequently asked questions about RF Front End IP cores
What is Quadrature former 75-750 MHz?
Quadrature former 75-750 MHz is a RF Front End IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this RF Front End?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RF Front End IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.