Quad MAC DSP core
ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications.
Overview
ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications. The compiler friendly architecture offers an orthogonal instruction set that greatly simplifies programming complex DSP algorithms and control code, with compact code density.
ZSPNano+ is ideally suited for applications requiring programmable, yet energy efficient signal processing solutions. It can achieve up to 3.5 GMacs/s worst case performance in 14nm technology. ZSPNano+ is supported by a comprehensive software development toolkit - ZView, that includes a C/C++ compiler, and can also support multi-core debug. VeriSilicon offers a broad portfolio of optimized software to help product developers from concept to market.
Key features
- Four 16b macs/cycle or Two 32b macs/cycle
- 8/16/32/64 data types
- SIMD support
- High precision (upto 72 bit accumulation)
- Low power modes of operation
- 128 bit data bandwidth
- TCM and Cache memories
- 4GB addressable space
- ZTurbo interface for custom accelerators
- Optional FPUs
- Optional MPU
Benefits
- Optimal performance, power, area balance
- Easy to program
- Easy to integrate into any SOC
- MCU+DSP capabilities
- Roadmap to higher performance ZSP Cores
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Arithmetic Unit IP cores
What is Quad MAC DSP core?
Quad MAC DSP core is a Arithmetic Units IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Arithmetic Units?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.