Vendor: Algo-Logic Systems Category: Arithmetic Units

Key Value Store/Exact Match Search Engine

The Ultra-Low-Latency (ULL) Exact Match Search Engine (EMSE) IP is latency-optimized Key-Value Store (KVS) system for Accelerated…

Overview

The Ultra-Low-Latency (ULL) Exact Match Search Engine (EMSE) IP is latency-optimized Key-Value Store (KVS) system for Accelerated Finance applications. Algo-Logic leverages FPGA Accelerations to deliver extreme look-up and IOP performance.  EMSE core has the unique ability to maintain constant lookup time through an advanced table balancing algorithm input instead of a variable lookup delays common with trees and/or hash probing algorithms.

​EMSE can be used either as a stand-alone FPGA IP using the hardware command interface or with an API so that data can be shared between software and logic on FPGA.

Key features

  • Supports following commands in logic and software
    • Insert {Key, Value}
    • Value = Search {Key}
    • Modify {Key, Value}
    • Delete {Key}
  • Parameterizable field and table sizes
    • Key sizes between 80 to 640 bits
    • Value sizes in increments of 8 bits
    • Number of entries
  • Support for larger on-chip tables
    • Large tables can be stored using UltraRAM in Xilinx UltraScale+ device family
  • Sharing data between logic and software
    • Hardware interface enables issuing commands from FPGA logic
    • C++ software API enables issuing commands from software
  • Core tracks usage statistics

Block Diagram

Applications

  • High Frequency Trading
  • Tick-To-Trade systems
  • Pre-Trade Risk Check systems
  • Position and Exposure tracking

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
EMSE
Vendor
Algo-Logic Systems
Type
Silicon IP

Provider

Algo-Logic Systems
HQ: USA
Algo-Logic maps trading algorithms into Field Programmable Gate Array (FPGA) logic. Algo-Logic's accelerated finance products augment existing futures and options Order Management System (OMS) software to provide ultra low latency for time-critical trades. Algo-Logic's Tick-to-Trade (T2T) systems and FPGA-as-a-Service are used by multiple proprietary trading firms and market makers to enhance profitability and reduce risk due to slippage. Algo-Logic's development framework includes implementations the Ethernet MAC, TCP/IP transport protocol, and Key-Value-Store (KVS) in logic to process network packets with deep sub-microsecond latency. Algo-Logic is partnered with Cisco, AMD/Xilinx, and Intel/Altera to provide solutions that run on multiple platforms.

Learn more about Arithmetic Units IP core

A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)

This article provides an in-depth analysis of the specific PPA challenges introduced by PQC and elucidates how PUF-PQC leverages its unique dualtrack strategy to deliver a robust and flexible Hardware Root of Trust (HRoT) across diverse application scenarios. Furthermore, it demonstrates the integration of Physical Unclonable Function (PUF) with a NIST SP 800-90B compliant True Random Number Generator (TRNG) to serve as critical components of PUFrt (Root of Trust), ensuring the security of post-quantum key generation starting from the entropy source.

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational—are time-consuming, error-prone, and heavily reliant on manual expertise. With growing design complexity and shrinking time-to-market, the need for automation in digital design is more critical than ever.

LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register Usage

Given the prominence of the LTE protocol in wireless devices, it is surprising that there are very few DFT FPGA circuit implementations from which to choose. This is likely due to the complexity of the circuit, which must accommodate run-time choice of many and large non-power-of-two transforms, requiring multiple radices for efficient DFT calculation.

FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus

DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design.

Frequently asked questions about Arithmetic Unit IP cores

What is Key Value Store/Exact Match Search Engine?

Key Value Store/Exact Match Search Engine is a Arithmetic Units IP core from Algo-Logic Systems listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP