Vendor: NetTimeLogic GmbH Category: IEEE-1588 / PTP

Pulse Per Second (PPS) Clock to PPS core

NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configura…

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Overview

NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configurable frequency, it is intended to be connected to a PPS Slave core able to syntonize to a Pulse per Second. The core also checks if the input clock is in the configured range and only if so will generate a PPS. The core can be configured either by signals or by an AXI4Lite-Slave Register interface.

This core is intended to be used with either external clocks or also SyncE clocks when the frequency shall be adjusted numerically rather than a clock switch.

Key features

  • Configurable input frequency from 100Hz to 100MHz
  • Input frequency supervision
  • PPS duty cycle configurable in ms steps
  • PPS Generation runs directly on Input Clock (minimal Jitter)
  • AXI4Lite register set or static configuration

Block Diagram

NTL_PPS_CLK_TO_PPS block diagram

Benefits

  • Coprocessor handling PPS generation standalone in the core.
  • Wide frequency input and runtime configurable.
  • Allows to have a syntonized clock even if the input clock is gone
  • Simple interface

Applications

  • Legacy Networks
  • Time converters
  • Robot control
  • Distributed data acquisition
  • Test and measurement

What’s Included?

  • Source Code (not encrypted, not obfuscated)
  • Reference Designs
  • Testbench with Stimulifiles
  • Configuration Tool
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
NTL_PPS_CLK_TO_PPS
Vendor
NetTimeLogic GmbH

Provider

NetTimeLogic GmbH
HQ: Switzerland
NetTimeLogic offers full time synchronization, network redundancy, and time sensitive networking solutions as vendor independent FPGA IP cores and design services in these fields. We provide full hardware implementations of synchronization IP cores such as PTP-Transparent-, Ordinary-, Grandmaster- or Hybrid-Clocks as well as IRIG-, PPS-, NMEA-Masters and Slaves, a NTP Server and Client and a RTC-Master and a DCF-Slave. For network redundancy we provide a full hardware implementation of the HSR and PRP protocols and for time sensitive networking we provide also a full hardware implementation of TSN suporting all major standards. All IP cores can be combined to a complete synchronization or network redundancy solution which can act e.g. as bridge between the different times synchronization protocols or as a network redundancy solution with time synchronization support. We also offer design services in the field of FPGA and Embedded Software development. With our 20+ years of experience and certification in FPGA and software development as well as product and project management we bring in our expertise to design the best possible solution for you. We understand your needs and can give you support to develop a best in class product. We offer swiss quality engineering - highest quality, always on time!
Contact NetTimeLogic GmbH

Learn more about IEEE-1588 / PTP IP core

Seize the Ethernet TSN Opportunity

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Frequently asked questions about Time Synchronization IP cores

What is Pulse Per Second (PPS) Clock to PPS core?

Pulse Per Second (PPS) Clock to PPS core is a IEEE-1588 / PTP IP core from NetTimeLogic GmbH listed on Semi IP Hub.

How should engineers evaluate this IEEE-1588 / PTP?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this IEEE-1588 / PTP IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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