Vendor: Xilinx, Inc. Category: Protocol Bridge

PLBV46 to AXI Bridge

The Processor Local Bus (PLB v4.6) to AMBA® ( Microcontroller Bus Architecture) eXtensible Interface (AXI) Bridge translates PLBV…

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Overview

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters.

Key features

  • Connects as a 32/64-bit slave on PLB v4.6 buses of 32, 64 or 128 bits
  • Supports 1:1 (PLB:AXI) synchronous clock ratio
  • Supports access by 32, 64-bit PLB masters
  • Single transfers of 1 to 8 bytes
  • Optional line transfers of 4 and 8 words
  • Optional Fixed length burst transfers of 2 to 16 data beats of words and double words
  • Supports optional two levels of address pipelining
  • Supports split bus architecture (simultaneous read and write operations)
  • Supports optional PLB status/interrupt registers and generates interrupts

Specifications

Identity

Part Number
PLBV46 to AXI Bridge
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about Protocol Bridge IP cores

What is PLBV46 to AXI Bridge?

PLBV46 to AXI Bridge is a Protocol Bridge IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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