UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Vendor:
Xilinx, Inc.
Category:
Protocol Bridge
PLBv46 Endpoint Bridge for PCI Express
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core.
Overview
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core. The PLBv46 Endpoint sub-system provides full bridge functionality between the PLB bus architecture and the PCIe network. The sub-system is composed of the PCIe core, one GT interface and the PLBv46 Endpoint. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.
The PLBv46 Endpoint provides a transaction level translation of PLB bus commands to PCIe TLP packets and PCIe requests to PLB bus commands.
The PLBv46 Endpoint provides a transaction level translation of PLB bus commands to PCIe TLP packets and PCIe requests to PLB bus commands.
Key features
- Endpoint only
- Support PLB memory access to PCIe memory
- Provide PLB master access for PCIe devices
- Translate PLB transactions to appropriate PCIe
- Transaction Layer Packets (TLP) packets
- Track and Manage TLPs that require completion processing
- Indicate error conditions detected by the PCIe core through interrupts
- Supports up to 3 remote PLB memory regions mapped to PCIe address space
- Address spaces are defined with a base address, an upper address, and an address translation value
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
PLBv46 Endpoint Bridge for PCI Express
Vendor
Xilinx, Inc.
Type
Silicon IP
Provider
Xilinx, Inc.
HQ:
USA
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Frequently asked questions about Protocol Bridge IP cores
What is PLBv46 Endpoint Bridge for PCI Express?
PLBv46 Endpoint Bridge for PCI Express is a Protocol Bridge IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.