Phase-frequency detector in CMOS logic
The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full …
Overview
The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full swing CMOS signal and two D-flip-flops with reset, made in CMOS logic. Multiplexer allows to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
Key features
- AMS BiCMOS 0.35 um
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100 MHz
- Differential CMOS output signal
- CMOS output signal for lock detector
- Built-in reset delay circuit
- Portable to other technologies (upon request)
Block Diagram
Applications
- Phase-locked loop synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about PLL IP cores
What is Phase-frequency detector in CMOS logic?
Phase-frequency detector in CMOS logic is a PLL IP core from NTLab listed on Semi IP Hub.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.