Vendor: Silicon Creations Category: PLL

High Quality LC-PLLs

Silicon Creations provides precise, ultra-low jitter LC-tank based PLLs for demanding applications such as AFE, Converter, high-e…

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Overview

Silicon Creations provides precise, ultra-low jitter LC-tank based PLLs for demanding applications such as AFE, Converter, high-end PHY and RF clocking. Our LC-PLL portfolio includes: 

  • Advanced Fractional-N LC-PLLs with all digital architecture supporting an LC-Tank are proven in 7nm FinFET and commencing production. These IPs are low power (below 10mW), small (below 0.1mm2) and can provide broadband jitter comfortably below 300fs RMS.
  • 28nm Fractional-N synthesizers in production in TSMC, UMC and SMIC with generated LTJ below 500fs RMS broadband and below 150fs RMS integrated above 1MHz.

Key features

  •  Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
  •  Passes PCIe6 reference clock requirements with wide margin
  •  Reference spur <200fs RMS
  •  Random period jitter <30fs RMS
  •  Low-leakage standby mode for fast re-locking
    •  “Instant” frequency lock from standby
    •  < 0.1% frequency error over PVT for open-loop DCO
  •  ±8% frequency tuning range
  •  Programmable loop bandwidth

Block Diagram

LC-PLLs block diagram

Benefits

  • Saves power and system cost:
  • Replaces expensive (>$10) external jitter cleaner PLL chips requiring off-chip differential buffers and receivers with silicon area costing just a few cents.
  • Reduces risk.

Applications

  • Clock de-spreading for Video format converters.
  • Jitter cleaning for Synchronous Ethernet and Gapped Clock cleaning in OTU systems

What’s Included?

  • Synthesizable RTL (Verilog)
  • Timing constraints
  • Documentation
  • Comprehensive support

Specifications

Identity

Part Number
LC-PLLs
Vendor
Silicon Creations
Type
Silicon IP

Provider

Silicon Creations
HQ: USA
Silicon Creations provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), SerDes and high-speed differential I/Os. Silicon Creations' IP is in production from 5nm to 180nm for diverse applications including smart phones, wearables, consumer devices, processors, network devices and medical devices. With a complete commitment to customer success, Silicon Creations’ IP has an excellent record of first silicon to mass production in over 500 chips for over 220 customers and has earned “best-of” awards from TSMC and SMIC. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, USA, and Krakow, Poland, and worldwide sales representation.
Contact Silicon Creations

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is High Quality LC-PLLs?

High Quality LC-PLLs is a PLL IP core from Silicon Creations listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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