Vendor: Obsidian Technology Category: PLL

General Purpose PLL for VIS 150nm

The OT3122v150 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for …

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VIS 150nm Silicon Proven View all specifications

Overview

The OT3122v150 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the VIS 0.15µ digital, mixed signal, or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for exceptional cycle to cycle jitter performance.

This function is also available for TSMC 130nm, TSMC 152nm, TSMC 180nm, IBM 180nm, and ams 180nm.

Key features

  • Wide range N, M, P integer dividers.
  • 40MHz – 600MHz output frequency range.
  • Comparable frequency range 8MHz – 50MHz.
  • 18pS RMS cycle to cycle jitter at 600MHz.
  • Lock-detect function.
  • Bypass function.
  • Well defined startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.06mm2 in 0.18µ CMOS.
  • 1.5mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.18µ CMOS process compatibility.
  • Only 1.8V transistors are used in the design.
  • Silicon proven.

Block Diagram

OT3122v150 block diagram

Applications

  • Crystal frequency to device internal clock multiplicatiion.
  • Communication cores.
  • Bus Interface cores.

What’s Included?

  • Verilog model.
  • CDL netlist for LVS.
  • Design review documentation.
  • GDS format layout.
  • Timing files.
  • Integration notes.
  • Production test notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
VIS 150nm 150nm 1500 nm Silicon Proven

Specifications

Identity

Part Number
OT3122v150
Vendor
Obsidian Technology

Provider

Obsidian Technology
HQ: USA
About Obsidian Technology
  • Founded 1995
  • Privately owned consulting company
  • Diversified customer base
  • Self funded
About Obsidian IP
  • Early delivery of front-end models.
  • On-site support available, including transfer of source to your design environment.
  • Available on-site design review.
  • On-site training for source licensing.
  • Option to take ip though your own quality and review processes.
  • Characterization support.
  • Fast and flexible legal. We typically accept your standard bi-directional NDA.
  • Simple plain-language contracts.
Contact Obsidian Technology

Learn more about PLL IP core

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Specifying a PLL Part 2: Jitter Basics

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In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is General Purpose PLL for VIS 150nm?

General Purpose PLL for VIS 150nm is a PLL IP core from Obsidian Technology listed on Semi IP Hub. It is listed with support for vis Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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