Vendor: Cadence Design Systems, Inc. Category: Network-On-Chip

NoC System IP

The Janus Network on Chip (NoC) is a new configurable soft IP designed to speed up the system-on-chip (SoC) and full system desig…

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Overview

The Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs.

With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce challenges to physical designs, specifically when routing large numbers of wires and meeting clock speed targets.

The Janus NoC addresses those challenges by employing multiple strategies:

  • Packetization allows a reduction of the wire count
  • Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
  • Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster

Key features

  • Reduces wire count and congestion
  • Reduces physical design issues
  • Handles gear change automatically
  • Configurable to meet your PPA goals
  • Easy to configure with a quick turnaround of configuration changes
  • Use with Cadence simulation/emulation to identify bottlenecks and remove them

Block Diagram

Janus NoC block diagram

Benefits

  • Intuitive Design Entry Tool
    • Use a powerful GUI to generate a NoC configuration, then submit the configuration to get RTL and SystemC models
  • Highly Configurable
    • Configure BW, latency, clock domain crossings, clock gating, buffer size, and pipeline stages—everything you need to achieve your target PPA goals
  • Scalability
    • Start with subsystem design, then take the same design and create a full SoC; Need a higher level of integration? No problem, we can do chiplets as well

Files

Product Sheet Download

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Specifications

Identity

Part Number
Janus NoC
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Frequently asked questions about NoC IP cores

What is NoC System IP?

NoC System IP is a Network-On-Chip IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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