Overview
The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs. AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4.
Mobiveil Inc. a proven Silicon IP provider for SSD Storage domain and High speed IO connectivity is offering proven AXI Interconnect IP solution for use in SOC applications. With this IP addition, Mobiveil offers complete set of IPs needed for accelerated SOC development that includes PCIe, DDR/LPDDR, Toggle/NAND, RISC-V Core, Interrupt Controller, QSPI, I2C, UART, GPIO, AXI-APB Bridge and Timer.
Provider
Mobiveil is a fast-growing Technology company that specializes in creation of Intellectual Properties, Application Platforms and solutions for Flash Storage, wired and wireless communications, IoT, Industrial and Robotics
The Mobiveil team leverages decades of experience in delivering high-quality, production-proven, high-speed serial interconnect Silicon IP cores to the leading customers worldwide. With a highly motivated engineering team, dedicated integration support, flexible business models, strong industry presence through strategic alliances and key partnerships, Mobiveil solutions have added tremendous value to the customers in executing their marketing and engineering goals within budget and on time.
Mobiveil is headquartered in the Silicon Valley with engineering development centers located in Milpitas, CA, Chennai, Bangalore, Hyderabad and Rajkot India, and sales offices and representatives located in US, Europe, Israel, Japan, Taiwan and People Republic of China.
If you are interested in choosing Mobiveil as your IP partner and would like to understand what's unique about our IP offerings, receive our whitepaper - "What it takes to deliver a configurable and quality Silicon IP." To get your copy write to us at ip@mobiveil.com (We recommend you use your corporate email address please)
Learn more about Network-On-Chip IP core
Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.
Microcontrollers (MCUs) are no longer the humble workhorses of embedded systems. Today’s MCUs rapidly evolve into compact, high-performance computing platforms, integrating artificial intelligence (AI), advanced security features, and real-time processing into power-constrained environments.
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.
In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.
Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.
