MIPI D-PHY Bidir 2/4L

The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-PHY interface. The MIPI D-PHY Bidir 2/4L is stacked in a configuration with two/four data lanes and one clock lane. The MIPI D-PHY Bidir 2/4L can be reused for both master and slave applications. The lane modules are bidirectional with HS-TX, HS-RX, LP-TX, LP-RX, and LP-CD functions, but with no support for high-speed reverse communication. The MIPI D-PHY Bidir 2/4L also includes a clock multiplier PLL for high-speed (HS) clock generation needed in a master-side application. It is targeted for the digital data transmission between a host processor and display drivers or camera interfaces in mobile applications, supporting a maximum effective bit rate of 1.5 Gbps per lane. Because of its dual master/slave reusability, the MIPI D-PHY Bidir 2/4L builds a bidirectional high-speed differential interface for serial data transmission. There is an additional reduced-throughput, low-power data transfer mode in each differential pair, which reduces line count and minimizes cable wires and EMI shielding requirements.

•  Attachable PLL clock multiplication unit for master-side functionality
•  Flexible input clock reference — 5 MHz to 500 MHz
•  50% DDR output clock duty-cycle
•  Lane operation ranging from 80 Mbps to 1.5 Gbps in forward direction
•  Aggregate throughput up to 3 Gbps with two data lanes, 6 Gbps with four data lanes
•  PHY-Protocol Interface (PPI) for clock and data lanes
•  Low-power Escape modes and Ultra Low Power state
•  2.5 V ± 10% analog supply operation
•  1.1 V ± 10% digital supply operation

• We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.