Vendor: Weasic Microelectronics Category: PLL

Low Power 300-600 MHz programmable PLL

The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply.

Contact Provider Request Datasheet
GlobalFoundries 22nm FDX View all specifications

Overview

The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply. This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz. The VCO outputs are coming into 8 cascaded phases. The PLL needs a sourcing current of 2 uA in order to operate. In the PLL logic, scan chain has been implemented for complete IP testability.

Key features

  • Layout Area: 460 um X 290 um
  • Low Power PLL
  • PN (SSB): -80 dBc/Hz at Δf = 1 MHz
  • Reference input: 16 MHz to 50 MHz
  • Power Dissipation: 1.5 mW
  • Output frequency range: 360 MHz to 600 MHz
  • Lock time: < 50 us
  • Ring-VCOs with 128 Bands
  • Automatic VCO/Band Selection System
  •  

Block Diagram

WEAPLL400M22 block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX —

Specifications

Identity

Part Number
WEAPLL400M22
Vendor
Weasic Microelectronics

Provider

Weasic Microelectronics
HQ: Greece
Weasic develops and markets mmWave Analog and Mixed-Signal IP for 5G backhaul, Automotive RADARs and Satellite Radios. Weasic’s world class design team has a strong record of successfully delivering first-pass silicon for the most challenging design specifications in performance, power consumption and silicon area. Weasic’s IP is in production with multiple customers world-wide, including some of the largest names in the industry sectors we serve. Weasic was founded in 2014 and is based in Athens, Greece.
Contact Weasic Microelectronics

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Low Power 300-600 MHz programmable PLL?

Low Power 300-600 MHz programmable PLL is a PLL IP core from Weasic Microelectronics listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP