Vendor: UniIC Category: PLL

Integer-N PLL, 32M ~ 256MHz on UMC 55nm

This present IP is a Phase Locked Loop (PLL) circuit.

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UMC 55nm View all specifications

Overview

This present IP is a Phase Locked Loop (PLL) circuit. It’s analog PLL suitable for various frequency node generations. The VCO can run from 32MHz to 256MHz. It contains input clock divider (DIVM), a feedback clock divider (DIVN) and level shifter block to switch signals between VDD12 and VDD33. It’s integer PLL, the output clock will be locked at different multiples of the input frequency_x000D_

A Lock indicator block (LOCK DECT) is also included in this PLL. It’s shows whether the output clock is at the right multiples of the input clock. DFT block is also employed to mux the internal nodes to outside for debug purpose.

Key features

  • Input reference frequency range from 4MHz-25MHz.
  • Frequency of vco: 32MHz~256MHz.
  • Process: UMC 55nm ULP Process
  • Supply voltage: VDD33: 1.8v~3.6v, VDD12: 1.2v±10%.
  • Operation Temperature: Tj = -40℃ ~ +125℃

Silicon Options

Foundry Node Process Maturity
UMC 55nm 55nm 550 nm —

Specifications

Identity

Part Number
Integer-N PLL, 32M ~ 256MHz on UMC 55nm
Vendor
UniIC

Provider

UniIC
HQ: China
Xi'an UniIC, a subsidiary of Tsinghua Unigroup, is a product and service provider focusing on DRAM (Dynamic Random Access Memory) technologies. As a technology-driven comprehensive IC design enterprise, its core business includes standard memory chips, module and system products, embedded DRAM and memory controller chips, as well as ASIC design services.
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Learn more about PLL IP core

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Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

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In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Integer-N PLL, 32M ~ 256MHz on UMC 55nm?

Integer-N PLL, 32M ~ 256MHz on UMC 55nm is a PLL IP core from UniIC listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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