Vendor:
SmartDV Technologies
Category:
LIN
LIN Synthesizable Transactor
LIN Synthesizable Transactor provides a smart way to verify the LIN component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
LIN Synthesizable Transactor provides a smart way to verify the LIN component of a SOC or a ASIC in Emulator or FPGA platform. Local Interconnect Network (LIN) Synthesizable Transactor is a single-wire, serial communication protocol based on the UART interface that is gaining popularity as a sub-bus standard in the automotive industry. LIN Transactor are reusable components that provide ready made verification environment. Compatible with Local Interconnect Network (LIN) specifications version 2.2A and supports all the frame types such as Unconditional, Event-triggered, Sporadic, Diagnostic and Reserved frames.
LIN 2.2A Synthesizable Transactor includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.
Key features
- Compatible with Local Interconnect Network (LIN) specifications version 2.2A
- Compliant with ISO/DIS 17987-2, ISO/DIS 17987-3 and ISO/DIS 17987-4
- Supports test cases as per standard
- INTERNATIONAL STANDARD ISO/DIS 17987-6
- Supports Unconditional, Event- triggered, Sporadic and Diagnostic frames
- Unconditional frames
- Event-triggered frames
- Sporadic frames
- Diagnostics frames
- Reserved frames
- Supports programmable clock frequency of operation
- Simulates LIN cluster with number of nodes the user requires
- These LIN nodes can be configured as Master or Slave nodes
- The DUT can either be a LIN 2.2A master or slave device
- Supports cluster wake up and go to sleep
- Supports all types of error insertion and detection
- Checksum error
- Parity error
- Oversize error
- PID start/stop error
- Sync start/stop error
- Break length error
- Delimiter error
- Diagnostic frame errors
- Supports glitch insertion and detection
Block Diagram
LIN Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the LIN testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
LIN Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Learn more about LIN IP core
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Frequently asked questions about LIN IP cores
What is LIN Synthesizable Transactor?
LIN Synthesizable Transactor is a LIN IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this LIN?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LIN IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.