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ChipCraft is a private fabless semiconductor manufacturer that specializes in GNSS technology. The company provides fully integrated, multi-frequency, multi-constellation GNSS receivers of high precision and reliability. The NaviSoC receiver is offered as a chip and as a module, and is dedicated to consumer, industrial and automotive markets. ChipCraft also offers custom silicon design and development services for ASIC and FPGA, as well as silicon-proven IP blocks and IP cores, for multimarket sectors. The company is headquartered in Warsaw, Poland and supports customers worldwide.
ChipCraft offers custom silicon design services for ASIC and FPGA. Our highly experienced, multi-disciplinary development team consists of system and processor architects, system micro-architects, VLSI designers, verification engineers and embedded software designers, as well as experts in communication systems, satellite navigation and signal processing. ChipCraft provides turnkey solutions based on full-flow IC design services. Our team can also deliver custom IP blocks or sub-systems, as well as augment any design team with required expertise. The Warsaw-based company has been providing effective design services and silicon-proven IP since its founding in 2016.
ChipCraft’s flagship product the NaviSoC is a GNSS receiver integrated with an application processor on a single silicon die. The NaviSoC system on a chip delivers high precision, high reliability and security with low power consumption in a small size. The flexible solution offers customization to user requirements. The product serves variety of applications, including LBS, IoT, Lane-level Navigation, UAV and Autonomous Drones, Asset tracking, Time Synchronization, Smart Agriculture, Surveying and Mapping.
Learn more about Mixed Signal Subsystem IP core
Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.
This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip. We combine a top-down functional approach, based on early system-level modelling, with a bottom-up performance approach based on transistor level simulations, in an agile development methodology. We look at how real valued modelling, using the Verilog-AMS wire that carries a real value (wreal) data type, achieves shorter simulation times in large SoCs with high frequency RF sections, low bandwidth analogue base-band sections and appreciable digital functionality including filtering and calibration blocks.
This paper discusses verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, the verification strategy is shown. The strategy is explained from the top level point of view, and detailed description is covered in subsequent sections. In following sections the system level testbench and interoperability testbenches are explained parallel to local testbenches for analog block characterization.
Don Dingee
This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
