Vendor: UniIC Category: PLL

Integer-N PLL, 600M-2.4G on SMIC 40nm

This present IP is a self-biased Phase Locked Loop (PLL) circuit, which can cover 600MHz-2.4GHz vco output frequency.

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SMIC 40nm Silicon Proven View all specifications

Overview

This present IP is a self-biased Phase Locked Loop (PLL) circuit, which can cover 600MHz-2.4GHz vco output frequency. It can generate adjustable clock from input signal by change the dividers’ value. There are two same post dividers following vco with ratio 1, 2, 4, 8, 16.

Key features

  • Input reference frequency range from 4MHz-40MHz.
  • Frequency of vco: 600MHz~2400MHz.
  • Process: SMIC40 Low Leakage Process
  • small area
  • Operation Temperature: Tj = -40℃ ~ +125℃

Silicon Options

Foundry Node Process Maturity
SMIC 40nm 40nm 400 nm Silicon Proven

Specifications

Identity

Part Number
Integer-N PLL, 600M-2.4G on SMIC 40nm
Vendor
UniIC

Provider

UniIC
HQ: China
Xi'an UniIC, a subsidiary of Tsinghua Unigroup, is a product and service provider focusing on DRAM (Dynamic Random Access Memory) technologies. As a technology-driven comprehensive IC design enterprise, its core business includes standard memory chips, module and system products, embedded DRAM and memory controller chips, as well as ASIC design services.
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Learn more about PLL IP core

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How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Integer-N PLL, 600M-2.4G on SMIC 40nm?

Integer-N PLL, 600M-2.4G on SMIC 40nm is a PLL IP core from UniIC listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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