Overview
Integrating advanced on-the-fly coordinate transformation and image processing powered by GPU technologies - High-performance image warping IP (distortion correction IP product)
TAKUMI’s Image Warping IP lines up hardware acceleration IP products that support a variety of different image warping/transform applications and their on-the-fly processing.
TW330 has realized real-time coordinate transformation and lens distortion correction at the same time with the newly integrated Geometry Engine.
Additionally, by supporting multiple core configurations (e.g., 2- or 4-core), TW330 will flexibly meet your diversified performance requirements.
TW330 also supports Bicubic filtration as a sampling filter for all color channels.
Image Warping IPs can correct distorted images captured through a wide-angle or fish-eye lens on different digital camera products, which also enables highly efficient and on-the-fly processing of image transformation at a video output from in-car head-up displays, projectors, or VR applications.
Learn more about Image Conversion IP core
Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.
Traditional IC design options that embedded system designers have had to choose from include fixed hardware devices such as standalone microprocessors, microcontrollers and ASSPs or configurable hardware devices such as FPGAs and cell-based ASICs. In this paper we present a new design option called Nextreme Structured ASICs which provide embedded system designers with a compelling alternative to custom embedded system design.
By Hantro
Configurable Processors for Video Processing SOCs
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
Beyond pure process scaling which is necessary to meet today's price, power, and performance goals, chip designers have to grapple with tighter integration and product performance specialities in areas such as integrated power management, image sensing, application-specific data conversion, and enhanced display drivers.
