I2C/I2S/LPC Verification IP
The I2C Verification IP provides an effective & efficient way to verify the components interfacing with I2C interface of an IP or…
Overview
The I2C Verification IP provides an effective & efficient way to verify the components interfacing with I2C interface of an IP or SoC. The I2C VIP is fully compliant with Rev. 6 of I2C specifications from Philips. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
Key features
- Fully compliant with Rev. 6 of the I2C-Bus Specification and backward compatible upto 2.1 version
- Full I2C Master and Slave functionality
- Master Transmitter/Master Receiver
- Slave Transmitter/Slave Receiver
- START, repeat START and STOP for all possible transfers
- Supports all Speed Modes: Standard Speed Mode (upto 100 kb/s), Fast Speed Mode (upto 400 kb/s), Fast Speed Mode Plus (upto 1Mb/s) and High Speed Mode (upto 3.4 Mb/s), Ultra fast mode (upto 5Mb/s)
- Supports 7-Bit and 10-Bit addressing format
- Allowstesting of varied bustraffic for Read, Write, General Call
- Supportsscoreboard feature for end to end data integrity check
- Notifies the Testbench of significant events such as transactions, warnings, and protocol errors
- Built in I2C Bus Monitor provides extensive protocol checking
- Supports Multi-Master and Multi-Slave system
- Supports Arbitration and Clock Synchronization
- Supports START Byte, Device ID, Bus Clear and Clock Stretching
- Supports various error injection and detection
- Provides verification scalability using functional coverage
- Provides logging facility for bus traffic in the ASCII format and in user configurable mode
- Supports Callback in Master and Slave
- Supports timing checks in the Monitor
- Supports UVM_RAL Model
- Supports CCI mode
- Supports transaction logging with detailed description of each transfer
Block Diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure the highest level of quality.
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
What’s Included?
- I2C Master / Slave Agent
- I2C Monitor and Score board
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual, and Release Notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
Learn more about I2S IP core
FPGAs - The Logical Solution to the Microcontroller Shortage
Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
Enabling AI Vision at the Edge
CSoC Platform / Digital Subsystem IP for IoT
Growing audio requirements in SoCs
Frequently asked questions about I2S IP cores
What is I2C/I2S/LPC Verification IP?
I2C/I2S/LPC Verification IP is a I2S IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this I2S?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2S IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.